Today's integrated circuit industry has produced a class of devices which operate from a relatively low voltage power source with relatively low power consumption. Most known integrated circuit families require an approximately five volt power source to operate properly. Three volt devices are becoming increasingly popular. The reduction in power source voltage requirements eases the demands on the power source. In other words, devices which operate at three volts are more readily adapted for use with power sources such as batteries than devices which operate at five volts. For most battery technologies, batteries which produce three volts are smaller and simpler than batteries which produce higher voltages. Many three volt single cell batteries are currently available. Since one goal in the design of three volt circuits is to maximize their usefulness with power sources with limited capacity, it is highly desirable to minimize current consumption of each circuit. The integrated circuit designer is therefore faced with the conflicting tasks of reducing the operating voltage of a circuit while at the same time minimizing the current requirements of the circuit.
Many integrated technologies have been readily adapted for operation at three volts. For example, three volt microprocessors and certain types of memory devices are currently available. However, electrically erasable read only memory (EEPROM) devices which operate at three volts with minimal current consumption have heretofore been impossible to manufacture. EEPROM devices provide non-volatile memory storage which may be accessed and altered using electrical signals which are typically generated by a microprocessor. Since the data stored in EEPROM devices is retained even in the absence of power, they are highly desirable for use in battery powered applications. However, EEPROM devices employ voltages for programming and erasing memory cells which do not exist in other integrated circuit technologies. For example, in one EEPROM family, a programming voltage in the range of twenty-five volts is required to program a memory cell.
While the twenty-five volt high voltage signal may be generated by "on-chip" circuitry, it is more difficult to generate twenty-five volts from a three volt power source than it is to generate it from a five volt power source. In addition, EEPROM devices employ negative voltages during operation in certain modes. In "floating gate" EEPROM devices, a three layer polysilicon and oxide structure may be used for nonvolatile memory storage. The EEPROM comprises a plurality of cells which incorporate this three layer polysilicon memory structure. One of the polysilicon layers is electrically insulated from the others and it is referred to as a "floating gate." The floating gate cooperates with a programming electrode which either places charge on or removes charge from the floating gate. As charge is placed on and removed from the floating gate, the three layer polysilicon structure is switched between conductive and non-conductive states. Since the floating gate is electrically insulated, whatever charge is placed on the floating gate will remain there until altered by the programming electrode. This type of EEPROM memory structure is typically referred to as a "thick-oxide EEPROM." For a detailed description of the operation of this type EEPROM memory, refer to U.S. Pat. No. 4,274,012, invented by Simko and assigned to the assignee of the present invention. This patent and all other U.S. Pat. Nos. mentioned below are incorporated herein by reference.
Since a thick oxide EEPROM structure depends on capacitive effects between the programming electrode and the floating gate, relatively high voltages, typically in the range of twenty-five volts, are required to program the floating gate. A typical input structure for EEPROM devices include a lateral NPNP structure formed with the substrate which may latch-up due to voltage undershoot caused by ringing in the system. If such a latch-up should occur, the memory device would consume a large amount of current. Unwanted effects may be introduced across adjacent cells when high voltage is present on the programming electrode (word lines). A latch-up is also possible whenever the voltage applied to the cell exceeds the field threshold of the parasitic transistors of the device. The field threshold is the gate voltage at which a parasitic thick oxide MOSFET turns on such that adjacent cells are no longer isolated from one another and therefore cannot be programmed and erased independently of one another.
It is known that the field threshold of a parasitic field-effect transistor is directly related to the bias voltage applied to the substrate of the cell. Specifically, as an increasingly negative voltage is applied to the substrate, the field threshold of a parasitic field transistor also rises. Specifically, in a typical thick-oxide EEPROM device, if zero volts are applied to the substrate, the parasitic field transistor will have a field threshold of approximately ten volts. Therefore, programming voltages in excess of ten volts may induce latch-up or cause incorrect programming in the device when the substrate bias is maintained at zero volts. If the substrate bias is maintained at -1 volts, the field threshold rises to approximately seventeen volts. Since thick-oxide memory cells require approximately twenty-five volts for accurate programming, a substrate voltage of between -2 volts and -3 volts is required to prevent data corruption and permit fully independent non-volatile operation of adjacent cells.
Since typical logic families today may operate from either three volts or five volts, devices which may be operated at both voltages are especially desirable. This complicates the design of thick oxide EEPROM devices. The generation of a -3 volt substrate bias voltage is not a significant problem when the circuit is operated from a five volt power source. However, when the voltage of the power source is reduced to three volts, the generation of -3 volts is particularly difficult for all known negative voltage bias generator topologies. Furthermore, known negative voltage bias generator topologies, if optimized for operation at three volts, produce excessively negative voltages if the positive power source voltage is raised to a higher voltage, thus resulting in unwanted and unnecessary current consumption.